Magnetoelectronic devices, spin electronic devices, and spintronic devices are synonymous terms for devices that make use of effects predominantly caused by electron spin. Magnetoelectronics are used in numerous information devices to provide non-volatile, reliable, radiation resistant, and high-density data storage and retrieval. The numerous magnetoelectronics information devices include, but are not limited to, Magnetoresistive Random Access Memory (MRAM), magnetic sensors, and read/write heads for disk drives.
Typically an MRAM includes an array of magnetoresistive memory elements. Each magnetoresistive memory element typically has a structure that includes multiple magnetic layers separated by various non-magnetic layers, such as a magnetic tunnel junction (MTJ), and exhibits an electrical resistance that depends on the magnetic state of the device. Information is stored as directions of magnetization vectors in the magnetic layers. Magnetization vectors in one magnetic layer are magnetically fixed or pinned, while the magnetization direction of another magnetic layer may be free to switch between the same and opposite directions that are called “parallel” and “antiparallel” states, respectively. Corresponding to the parallel and antiparallel magnetic states, the magnetic memory element has low (logic “0” state) and high (logic “1” state) electrical resistance states, respectively. Accordingly, a detection of the resistance allows a magnetoresistive memory element, such as an MTJ device, to provide information stored in the magnetic memory element. There are two completely different methods used to program the free layer: field switching and spin-torque switching. In field-switched MRAM, current carrying lines adjacent to the MTJ bit are used to generate magnetic fields that act on the free layer. In spin-torque MRAM, switching is accomplished with a current pulse through the MTJ itself. The angular momentum carried by the spin-polarized tunneling current causes reversal of the free layer, with the final state (parallel or antiparallel) determined by the polarity of the current pulse. A reset current pulse will cause the final state to be parallel or logic “0”. A set current pulse, in the opposite polarity of the reset current pulse, will cause the final state to be antiparallel or logic “1”. Spin-torque transfer is known to occur in MTJ devices and giant magnetoresistance devices that are patterned or otherwise arranged so that the current flows substantially perpendicular to the interfaces, and in simple wire-like structures when the current flows substantially perpendicular to a domain wall. Any such structure that exhibits magnetoresistance has the potential to be a spin-torque magnetoresistive memory element.
Spin-torque MRAM (ST-MRAM), also known as spin-torque-transfer RAM (STT-RAM), is an emerging memory technology with the potential for non-volatility with unlimited endurance and fast write speeds at much higher density than field-switched MRAM. Since ST-MRAM switching current requirements reduce with decreasing MTJ dimensions, ST-MRAM has the potential to scale nicely at even the most advanced technology nodes. However, increasing variability in MTJ resistance and sustaining relatively high switching currents through bit cell select devices in both current directions can limit the scalability of ST-MRAM.
An ST-MRAM array includes a plurality of core strips, with each core strip including a bit cell array comprising a plurality of columns of bit cells (a magnetic tunnel junction and a select transistor). Each column of a core strip is selected individually by a column select multiplexer controlled by a column address and each bit cell within the selected column is selected by the application of a voltage to the gate of the word line select transistor of that bit cell controlled by the row address. The number of address bits does not allow further selection of a single core strip out of a plurality of core strips because the multiple core strips in parallel each receive data from or provide data to a standard data path that is accessible by the user through data input or output pins. Even if the address bus is extended or time multiplexed to provide a core strip address, a separate decode circuit for core strip selection of a bit (magnetic tunnel junction) consumes a significant amount of space on the chip.
Often for test or failure analysis it is beneficial to know the resistance of a bit within a core strip of the bit cell array. This requires performing an analog read of the bit where voltage or current is applied to both terminals of the bit and a resulting current or voltage is measured. Additional selection circuitry needed to individually address each of a plurality of core strips for analog read circuitry reduces area on the chip for other functions.
Alternately, to debug noise issues in a chip, it is beneficial to selectively enable or disable a read or write operation to a bit within a core strip of the bit cell array. Selectively enabling the circuitry used to read or write a bit requires individually addressing each of the multiple core strips and the additional selection circuitry would add area to the chip.
Data stored in memory is often defined in banks. Access to a bank in a double data rate (DDR) memory generally includes an ACTIVATE operation, followed by several READ/WRITE operations and a PRECHARGE operation. The ACTIVATE operation opens a row (or page) of for example 1,000 or more bits. The READ/WRITE operation performs the reading or writing of columns, e.g., 128 bits, in the open row. The PRECHARGE operation closes the row.
During the ACTIVATE operation, a page of data is read from the memory array and stored in local data-store latch in the data path for subsequent READ and WRITE operations from and to the local data-store latch. The ACTIVATE operation can be initiated by an ACTIVATE command or any other command that performs the same operation. During a PRECHARGE operation, the data from local data-store latch is written back to the memory array, and as a result, that page is considered closed or not accessible without a new ACTIVATE operation. The PRECHARGE operation can be initiated by a PRECHARGE or AUTO-PRECHARGE command or any other command that performs the same operation.
DDR memory controllers may want to access less number of bits, for example 128 bits, than the full row or page, for example 1024 bits, of the memory. In such a case, the whole row or page must be opened during the ACTIVATE operation as known in the prior art. ACTIVATE operation consumes unnecessary power from reading the portion of a page that will not be accessed in subsequent READ or WRITE operations. Furthermore, a PRECHARGE operation must close that portion of a page as well contributing to unnecessary power consumption. Therefore, it is desirable to provide a method for selectively opening a portion of the page during an ACTIVATE operation, accessing the open portion of the page in subsequent READ or WRITE operations, and closing the same portion of the page with a PRECHARGE operation.
Accordingly, it is desirable to provide a method for selectively enabling the circuitry for performing an analog read, digital read, or write operation to a bit in a bit cell array during debug, test, and failure analysis while minimizing the added chip area by reusing elements of the standard data path. Furthermore, other desirable features and characteristics of the exemplary embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.